How to generate target RISC-V assembly code for OpenCL kernel in oneapi-construction-kit?

1

Hi,
Let’s say I have an OpenCL kernel like:

__kernel void addVectors( __global const float *a, __global const float *b, __global float *c) {	
  int gid = get_global_id(0);
  c[gid] = a[gid] + b[gid];
}

I would like to check the generated RISC-V ISA for RefSi G1 RV64 target (which is the software implementation in oneapi-construction-kit). I found there are two tools “clc” and “oclc”, but seems they can just generate binary file, not the asm code.

Another question is, I found the RefSi G1 RV64 target only has 1 compute unit, and doesn’t support vector extension, is there a target support multiple compute units and vector extension? Or is there any compatible hardware I can buy (like FPGA board or develop kit board)?

2

clc generates a binary that has a header before the actual elf file, if you do --strip-binary-header you will get the bare binary as an elf file which you can then dump using the appropriate tools.

We don’t currently support any specific hardware.

3

Huge thanks @colin.davidson , followed your advise, the riscv asm code can be generated with below command now.

$ clc --strip-binary-header vec_add_kernel.cl
$ llvm-objdump -d vec_add_kernel.bin > vec_add_kernel.asm